Method for semiconductor device having radiation hardened insulators and design structure thereof

ABSTRACT

A design structure is provided for a semiconductor device having radiation hardened buried insulators and isolation insulators in SOI technology. The device includes a first structure and a second structure. The first structure includes: a radiation hardened BOX layer under an active device layer; radiation hardened shallow trench isolation (STI) structures between active regions of the active device layer and above the radiation hardened BOX layer; metal interconnects in one or more interlevel dielectric layers above gates structures of the active regions. The second structure is bonded to the first structure. The second structure includes: a Si based substrate; a BOX layer on the substrate; a Si layer with active regions on the BOX; oxide filled STI structures between the active regions of the Si layer; and metal interconnects in one or more interlevel dielectric layers above gates structures. At least one metal interconnect is electrically connecting the first structure to the second structure.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to U.S. Ser. No. 12/186,750 filed on the same day and currently pending.

FIELD OF THE INVENTION

The invention relates to a design structure, and more particularly, to a design structure for a semiconductor device having radiation hardened buried insulators and isolation insulators in SOI technology.

BACKGROUND

Ionizing radiation can cause total failure resulting from total dose (long accumulation of radiation) in semiconductor ICs. In high radiation environments, such as space applications, ionizing radiation creates trapped charge and interface states in dielectric layers. That is, due to prolonged radiation exposure (total dose) a charge can build up at an interface between an oxide and SOI devices. This build up will eventually change the charge flow at the SOI interface. For example, trapped charge in the buried oxide (BOX) leads to increased backgate leakage and trapped charge in the STI increases leakage through the sidewall device. If the backgate or sidewall threshold voltage is allowed to move far enough from the design point, the circuitry can fail to operate.

Methods to prevent total dose include hardening the STI or BOX individually, which only addresses one possible means of failure. Consequently, there is a need to improve protection schemes from radiation events in ICs.

Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.

SUMMARY

In a first aspect of the invention, a device comprises a first structure and a second structure. The first structure comprises: a radiation hardened BOX layer under an active device layer; radiation hardened shallow trench isolation (STI) structures between active regions of the active device layer and above the radiation hardened BOX layer; metal interconnects in one or more interlevel dielectric layers above gates structures of the active regions. The second structure is bonded to the first structure. The second structure comprises: a Si based substrate; a BOX layer on the substrate; a Si layer with active regions on the BOX; oxide filled STI structures between the active regions of the Si layer; and metal interconnects in one or more interlevel dielectric layers above gates structures. At least one metal interconnect is electrically connecting the first structure to the second structure.

In a second aspect of the invention, a method in a computer-aided design system for generating a functional design model of a radiation hardened device, comprises: removing a substrate from an SOI wafer; selectively removing a buried oxide layer formed as a layer between the SOI wafer and active regions of a device; selectively removing isolation oxide formed between the active regions; and replacing the removed buried oxide layer and the isolation oxide with radiation hardened insulators, such as radiation hardened oxide.

In a third aspect of the invention, a design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit is provided. The design structure comprises a first structure and a second structure. The first structure comprises: a radiation hardened BOX layer under an active device layer; radiation hardened shallow trench isolation (STI) structures between active regions of the active device layer and above the radiation hardened BOX layer; metal interconnects in one or more interlevel dielectric layers above gates structures of the active regions. The second structure is bonded to the first structure. The second structure comprises: a Si based substrate; a BOX layer on the substrate; a Si layer with active regions on the BOX; oxide filled STI structures between the active regions of the Si layer; and metal interconnects in one or more interlevel dielectric layers above gates structures. At least one metal interconnect is electrically connecting the first structure to the second structure.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The present invention is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present invention.

FIGS. 1 and 2 show structures and respective processing steps in accordance with the invention;

FIG. 3 shows a final structure and respective processing steps in accordance with the invention;

FIG. 4 shows alternate processing steps to form an alternate final structure in accordance with the invention;

FIG. 5 shows an alternate final structure and respective processing steps in accordance with the invention; and

FIG. 6 is a flow diagram of a design process used in semiconductor design, manufacture, and/or test.

DETAILED DESCRIPTION

The invention relates to a design structure, and more particularly, to a design structure for a semiconductor device having radiation hardened buried insulation and isolation insulators in SOI technology. The radiation hardened insulator formed in the STI structure and BOX will prevent a charge build up at the interface between an insulator (STI or BOX) and the SOI devices due to prolonged radiation exposure (total dose) thus preventing a change in the charge flow at the SOI interface.

In embodiments, after an SOI wafer is processed including the formation of active devices separated by STI regions and interlevel dielectrics with metallization, for example, the substrate is removed to expose a BOX. The BOX and STI are then removed by a selective etch. A radiation hardened insulator is formed in the isolation trenches and below the active device layer, forming radiation hardened STI and BOX. In embodiments, the BOX is planarized. Advantageously, the processes of the invention are compatible with known 3D processes to form 3D integrated circuits. Compared to existing methods to harden buried and isolation oxides, this method has the advantage of hardening both the BOX and STI together.

Structures in Accordance with the Invention

FIG. 1 shows a beginning structure and respective processing steps in accordance with a first aspect of the invention. Specifically, FIG. 1 shows a BOX 12 formed on a wafer 10 such as, for example, a silicon substrate. In embodiments, the substrate 10 can be a few hundred microns and the BOX 12 can range from about 50 nm to 250 nm. As the structure thus far described is a conventional and commercially available structure, no further explanation is required herein.

Still referring to FIG. 1, a Si layer 14 is deposited on the BOX 12 in a conventional manner. The Si layer 14 may range from about 20 nm to 250 nm, depending on the technology, and will form the active regions of the device (active device layer). For example, the Si layer 14 may be about 20 nm to 100 nm for 45 nm technology; whereas, it may be increased upwards to about 250 nm for 130 nm or 150 nm technology. In an optional embodiment, a nitrogen layer 14 a can be deposited on the Si 14 as an etch stop layer.

In conventional lithographic and etching processes, shallow trenches are formed in the structure and more specifically in the Si layer 14. For example, a photolithographic masking layer (not shown) can be exposed to light to form openings, with a subsequent etching process (e.g., reactive ion etching (RIE)) to form the shallow trenches. A wet or dry resist/arc strip is used to remove the remains of the masking material. The shallow trenches will be used to form shallow trench isolation (STI) structures 16 which are filled with oxide material.

In conventional processing steps, a gate structure 18 and source and drain regions 20 are formed on the structure (above and in the active regions). The gate structure 18 may include, for example, a polysilicon gate formed on an oxide layer. The gate structure 18 may also include sidewalls/spacers comprising nitride or oxide or a combination thereof. The source and drain regions 20 may be formed using conventional doping methodologies, which do not need further explanation herein.

Interlevel dielectrics 22 are formed over the gate structure 18 and source and drain regions 20. Although two levels 22 are shown in FIG. 1, it should be understood by those of skill in the art that more or less than two levels are also contemplated by the invention, depending on a particular application. Metal interconnects 24 are formed in the dielectrics 22 using conventional damascene or dual damascene processes. The metal interconnects may be in contact with the source/drain regions and/or the gates, depending on a particular application.

FIG. 1 also shows a handle wafer 26 attached to the structure. The handler wafer 26 can be bonded to the structure in a conventional process.

FIG. 2 shows an intermediate structure and processing steps in accordance with the invention. As shown in FIG. 2, the substrate 10, BOX 12 and STI structures 16, e.g., oxide, are removed using conventional processes. For example, the substrate 10 will be removed using a grinding and selective etching process. The BOX 12 and STI structures 16, e.g., oxide, are removed using a selective oxide etch. The nitrogen layer 14 a may act as an etch stop to ensure that the etching of the BOX 12 and the STI structures 16 do not damage any other layers of the structure.

FIG. 3 shows a final structure and respective processing steps in accordance with the invention. Specifically, in FIG. 3, a radiation hardened insulator is deposited to form a radiation hardened BOX layer 28 and radiation hardened STI structures 30. The radiation hardened insulator may be, for example, a radiation hardened oxide such as a silicon rich oxide material. The deposition process may be a conventional CVD process. The BOX layer 28 can then be planarized using conventional processes. Advantageously, the radiation hardened insulator will not accumulate a charge in an ionizing environment thereby protecting the device from trapped charges which can lead to backgate leakage and increased leakage through the sidewall device.

In embodiments, the radiation hardened BOX layer 28 may be about 50 nm to 250 nm thick, depending on the technology. Also, due to the thickness of the Si layer 14, the radiation hardened STI structures 30 may be about 20 nm to 100 nm for 45 nm technology; whereas, it may be increased upwards to about 250 nm for 130 nm or 150 nm technology.

FIG. 4 shows an additional processing step to form a three dimensional structure in accordance with the invention. Specifically, FIG. 4 shows a stacking process using the structures of FIG. 1 and FIG. 3, for example. In FIG. 4, the BOX and STI of the lower wafer may be radiation-hardened by the same process steps used to radiation-harden the upper wafer, forming a 3D structure wherein all STI and BOX layers are radiation-hardened. Alternatively, the wafer-stacking process in FIG. 4 may be applied successively to form 3D structures with three or more active device layers. Alternatively, the structures may include more or less interlevel dielectrics and related metal interconnects. The stacking of the structures can advantageously be used with International Business Machine Corp.'s 3D assembly process as disclosed in “Three-dimensional integrated circuits”, by A. W. Topol et al. IBM J. RES. & DEV. Vol. 50, No. 4/5, July/September 2006, the contents of which are expressly incorporated by reference in its entirety herein.

FIG. 5 shows a stacked structure in accordance with the invention. In particular, the stacked structure can include the structures 100 and 200 shown in FIG. 1 and FIG. 3, respectively (including using more or less interlevel dielectric layers). The structures 100 and 200 may be bonded by one or more insulator or dielectric layers. The structures 100 and 200 are electrically connected by an interlevel wiring 32, formed through conventional etching and deposition methodologies.

The advantage of the structure of FIG. 5 is that sensitive circuits can be designed into the structure 200 of FIG. 3 (to prevent trapped charges) and less sensitive devices can be selectively designed into the structure 100 of FIG. 1. This can considerably reduce fabrication time and cost for applications that require radiation hardened materials. This also provides the advantage of having higher density devices, as the stack can include two or more structures.

Design Structure

FIG. 6 shows a block diagram of an exemplary design flow 900 used for example, in semiconductor design, manufacturing, and/or test. Design flow 900 may vary depending on the type of IC being designed. For example, a design flow 900 for building an application specific IC (ASIC) may differ from a design flow 900 for designing a standard component or from a design flow 900 for instantiating the design into a programmable array, for example a programmable gate array (PGA) or a field programmable gate array (FPGA) offered by Altera® Inc. or Xilinx® Inc. Design structure 920 is preferably an input to a design process 910 and may come from an IP provider, a core developer, or other design company or may be generated by the operator of the design flow, or from other sources. Design structure 920 comprises an embodiment of the invention as shown in FIGS. 3 and 5 in the form of schematics or HDL, a hardware-description language (e.g., Verilog, VHDL, C, etc.). Design structure 920 may be contained on one or more machine readable media. For example, design structure 920 may be a text file or a graphical representation of an embodiment of the invention as shown in FIGS. 3 and 5. Design process 910 preferably synthesizes (or translates) an embodiment of the invention as shown in FIGS. 3 and 5 into a netlist 980, where netlist 980 is, for example, a list of wires, transistors, logic gates, control circuits, I/O, models, etc. that describes the connections to other elements and circuits in an integrated circuit design and is recorded on at least one of machine readable medium. For example, the medium may be a CD, a compact flash, other flash memory, a packet of data to be sent via the Internet, or other networking suitable means. The synthesis may be an iterative process in which netlist 980 is resynthesized one or more times depending on design specifications and parameters for the circuit.

Design process 910 may include using a variety of inputs; for example, inputs from library elements 930 which may house a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.), design specifications 940, characterization data 950, verification data 960, design rules 970, and test data files 985 (which may include test patterns and other testing information). Design process 910 may further include, for example, standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc. One of ordinary skill in the art of integrated circuit design can appreciate the extent of possible electronic design automation tools and applications used in design process 910 without deviating from the scope and spirit of the invention. The design structure of the invention is not limited to any specific design flow.

Design process 910 preferably translates an embodiment of the invention as shown in FIGS. 3 and 5, along with any additional integrated circuit design or data (if applicable), into a second design structure 990. Design structure 990 resides on a storage medium in a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design structures). Design structure 990 may comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a semiconductor manufacturer to produce an embodiment of the invention as shown in FIGS. 3 and 5. Design structure 990 may then proceed to a stage 995 where, for example, design structure 990: proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc.

The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements, if any, in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated. 

1. A method in a storage medium computer-aided design system for generating a functional design model of a radiation hardened device, said method comprising instructions for: removing a substrate from an SOI wafer; selectively removing a buried oxide layer formed as a layer between the SOI wafer and active regions of a device; selectively removing isolation oxide formed between the active regions; and replacing the removed buried oxide layer and the isolation oxide with radiation hardened insulators as instructions in the design system.
 2. The design structure of claim 1, wherein the design structure comprises a netlist.
 3. The design structure of claim 1, wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.
 4. The design structure of claim 1, wherein the design structure resides in a programmable gate array.
 5. The design structure of claim 1, wherein the design structure includes at least one of test data, characterization data, verification data, or design specifications.
 6. A design structure embodied in a machine memory readable storage medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising executable instructions for formation of: a first structure comprising: a radiation hardened BOX layer under an active device layer; radiation hardened shallow trench isolation (STI) structures between active regions of the active device layer and above the radiation hardened BOX layer; metal interconnects in one or more interlevel dielectric layers above gates structures of the active regions; and a second structure bonded to the first structure, the second structure comprising: a Si based substrate; a BOX layer on the substrate: a Si layer with active regions on the BOX; oxide filled STI structures between the active regions of the Si layer; metal interconnects in one or more interlevel dielectric layers above gates structures; and at least one metal interconnect electrically connecting the first structure to the second structure as instructions in the design structure.
 7. The design structure of claim 6, wherein the design structure comprises a netlist.
 8. The design structure of claim 6, wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.
 9. The design structure of claim 6, wherein the design structure resides in a programmable gate array.
 10. The design structure of claim 6, wherein the design structure includes at least one of test data, characterization data, verification data, or design specifications. 